Semiconductor processing methods

ABSTRACT

The invention includes a semiconductor processing method in which a semiconductor substrate is exposed to reactive ion etching conditions. The reactive ion etching conditions comprise subjecting exposed surfaces of the substrate to a gas having components therein which are reactive with the exposed surfaces. A total concentration of the reactive components within the gas is less than 4.5%, by volume. In particular aspects, the total concentration of the reactive components can be less than 2% by volume, or less than 1% by volume. Exemplary reactive components are fluorine-containing components, such as NF 3 .

TECHNICAL FIELD

[0001] The invention pertains to semiconductor processing methods, andin particular application pertains to reactive ion etching ofsemiconductor substrates utilizing low concentrations of reactiveetching components.

BACKGROUND OF THE INVENTION

[0002] It is frequently desired during semiconductor processing to formopenings in a material. Prior to, or during, the formation of theopenings, a patterned mass (such as, for example, an antireflectivecoating), is frequently provided over the material. After the openingsare etched into the material, it is frequently desired to remove themass from over an upper surface of the material without extending adepth or width of the openings. This has proven difficult, and it wouldbe desirable to develop improved methods for removing a mass from overan upper surface of a material.

SUMMARY OF THE INVENTION

[0003] In one aspect, the invention encompasses a semiconductorprocessing method in which a semiconductor substrate is exposed toreactive ion etching conditions. The reactive ion etching conditionscomprise subjecting exposed surfaces of the substrate to a gas havingcomponents therein which are reactive with the exposed surfaces. A totalconcentration of the reactive components within the gas is less than4.5%, by volume. In particular aspects, the total concentration of thereactive components can be less than 2% by volume, or less than 1% byvolume. Exemplary reactive components are fluorine-containingcomponents, such as NF₃.

[0004] In one aspect, a semiconductor substrate includes a first mass ofmaterial, a second mass over the first mass, and an opening extendingthrough the first mass and into the second mass. The second mass has athickness and the opening has a width. The substrate is subjected toetching conditions which remove at least 250 angstroms from thethickness of the second mass, and which extend the width of the openingby no more than 100 angstroms, in some aspects by no more than 50angstroms; and in some aspects by no more than 10 angstroms. In furtheraspects, the etching conditions extend a depth of the opening by no morethan 50 angstroms, and in some aspects by no more than 10 angstroms.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Preferred embodiments of the invention are described below withreference to the following accompanying drawings.

[0006]FIG. 1 is a diagrammatic, cross-sectional view of a semiconductorwafer fragment at a preliminary processing step of a method of thepresent invention.

[0007]FIG. 2 is a view of the FIG. 1 wafer fragment shown at aprocessing step subsequent to that of FIG. 1.

[0008]FIG. 3 is a view of the FIG. 1 wafer fragment shown at aprocessing step subsequent to that of FIG. 2.

[0009]FIG. 4 is a view of the FIG. 1 wafer fragment shown at aprocessing step subsequent to that of FIG. 3.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] In particular aspects the invention includes methods in which abiased-substrate plasma is utilized at relatively high pressures (atleast 300 mTorr, and in some applications at least about 1000 mTorr) andlow reactive gas concentrations (less than 4.5% by volume, morepreferably less than 2% by volume, and even more preferably less than 1%by volume) to accomplish removal of a top layer of an integrated circuitconstruction without substantially effecting materials that are inexposed areas at the bottoms or sidewalls of high aspect ratio trenchesor contacts.

[0011] In particular aspects, the invention takes advantage of an etchlag to accomplish desired selectivity of etching various surfacefeatures relative to one another.

[0012] An exemplary method of the present invention is described withreference to FIGS. 1-4.

[0013] Referring initially to FIG. 1, a fragment of a semiconductorwafer construction 10 is illustrated. Wafer construction 10 comprises asubstrate 12, having an upper surface 15. Substrate 12 can comprise, forexample, monocrystalline silicon. To aid in interpretation of the claimsthat follow, the terms “semiconductive substrate” and “semiconductorsubstrate” are defined to mean any construction comprisingsemiconductive material, including, but not limited to, bulksemiconductive materials such as a semiconductive wafer (either alone orin assemblies comprising other materials thereon), and semiconductivematerial layers (either alone or in assemblies comprising othermaterials). The term “substrate” refers to any supporting structure,including, but not limited to, the semiconductive substrates describedabove.

[0014] An insulative material 14 is formed over substrate 12. Insulativematerial 14 can comprise, for example, borophosphosilicate glass (BPSG).

[0015] A mass 16 is formed over insulative material 14. Mass 16 can bean antireflective coating 16. Antireflective coating 16 can be, forexample, a dielectric antireflective coating (DARC), and can comprise,for example, silicon oxynitride (SiO_(x)N_(y), wherein x and y aregreater than zero).

[0016] A patterned masking layer 18 is formed over antireflectivecoating 16. Masking layer 18 can comprise, for example, photoresist, andcan be patterned utilizing photolithographic methods.

[0017] An opening 20 extends through patterned masking layer 18.

[0018] Referring to FIG. 2, opening 20 is extended throughantireflective coating layer 16 and insulative material 14, and to theupper surface 15 of substrate 12. Although opening 20 is shown extendingentirely through insulative mass 14, it is to be understood that opening20 can alternatively extend only partially into insulative mass 14.Also, it is to be understood that although opening 20 is shownterminating at upper surface 15 of substrate 12, the opening can alsoextend into substrate 12. In any event, opening 20 comprises a bottomperiphery 24, and sidewall peripheries 26.

[0019] An electrical node 22 is provided within substrate 12 byimplanting a conductivity-enhancing dopant through opening 20 and intothe semiconductive material of substrate 12. Electrical node 22 cancomprise either an n-type doped region or a p-type doped region.

[0020] It is to be understood that the methodology described withreference to FIGS. 1 and 2 for providing electrical node 22 at a base ofopening 20 is but one exemplary method, and that other methods can beutilized. For instance, electrical node 22 can comprise a conductiveplug formed over or within substrate 12 prior to formation of insulativematerial 14. Opening 20 can then be extended to an upper surface of theconductive plug. In such embodiments, the conductive plug can compriseone or more of conductively-doped silicon (such as polycrystallinesilicon), metal, and metal silicide, for example.

[0021] Opening 20 will preferably be a high aspect ratio opening, andspecifically will preferably will comprise an aspect ratio of at least3, more preferably of at least 5, yet more preferably of at least 6,even more preferably of at least about 6.5, and yet more preferably ofat least about 7. High aspect ratio openings are typically preferred insemiconductor processing applications over lower aspect ratio openings,in that higher aspect ratio openings consume a lower footprint ofvaluable semiconductor real estate than do lower aspect ratio openings.

[0022] Referring to FIG. 3, masking material 18 (FIG. 2) is removed toleave mass 16 over material 14. Mass 16 has a thickness “X”, and suchthickness can be, for example, at least 250 angstroms; in particularapplications at least 300 angstroms, and even at least 320 angstroms.

[0023] Opening 20 has a depth “D” within insulative material 14 and awidth “W”. An exemplary depth can be, for example, about 2 microns, andan exemplary width can be, for example, about 0.3 microns. Further,opening 20 can, in particular applications, comprise a circularperiphery, such that the width is a diameter of the circle.

[0024] In particular aspects of the invention, material 14 can beconsidered a first mass, coating 16 a second mass, and substrate 12 athird mass. Accordingly, opening 20 can be considered to extend throughfirst and second masses 14 and 16, and to terminate proximate surface 15of third mass 12. Alternatively, masses 12, 14 and 16 can be considereda first material, second material and third material, respectively; andopening 20 can be considered to extend through second and thirdmaterials 14 and 16, and to terminate proximate surface 15 of firstmaterial 12.

[0025] Wafer 10 is subsequently exposed to etching conditions whichremove a substantial portion of material 16 from over mass 14. Inparticular embodiments, an entirety of material 16 is removed to formthe resulting structure shown in FIG. 4. The etching conditionspreferably comprise reactive ion etching conditions in which exposedsurfaces of wafer 10 are subjected to a gas having components thereinwhich are reactive with material 16. The components can also be reactivewith exposed portions of materials 12 and 14. In particularapplications, the reactive components can comprise fluorine-containingmolecules, such as, for example, NF₃. A total concentration of thereactive components within the gas utilized for reactive etching ofmaterial 16 is preferably less than 4.5%, by volume; more preferablyless than 2%, by volume; and even more preferably less than 1%, byvolume.

[0026] The reactive ion etching of material 16 will typically occurwithin a reactive ion etch plasma reactor, and preferably a pressurewithin the reactor to which wafer 10 is exposed during etching ofmaterial 16 will be from about 300 mTorr to about 1000 mTorr. Further,wafer 10 will preferably be subjected to a bias of from about 50 wattsto about 2000 watts in the reactive ion etch plasma reactor duringetching of material 16, and can be subjected to an exemplary bias offrom about 50 watts to about 500 watts, or from about 350 watts to about400 watts. A suitable reactor is the Iridia™ reactor marketed byNovellus Systems, Inc.

[0027] The above-described etching conditions are substantiallydifferent than the conditions typically utilized within a reactive ionetch reactor. Specifically, etching within reactive ion reactors wouldtypically be conducted at a pressure of less than 200 mTorr, and with areactive gas concentration of from about 5% to about 100%, by volume.However, the typical reactive ion etch will remove large amounts ofmaterial from exposed surfaces within an opening (such as opening 20),as well as from exposed upper surfaces of wafer 10. In contrast,methodology of the present invention can substantially selectivelyremove material 16 from exposed upper surfaces of wafer 10, while notremoving material from within opening 20. More specifically, methodologyof the present invention can remove at least 250 angstroms of material16 from over mass 14 while extending the depth “D” of opening 20 by nomore than 50 angstroms. In particular embodiments, at least 300angstroms of material 16 can be removed from over mass 14, or least 320angstroms of material 16 can be removed from over mass 14, while notextending the depth “D” of opening 20 by more than 50 angstroms; and infurther embodiments an entirety of material 16 can be removed from overmass 14 while not extending the depth “D” of opening 20 by more than 50angstroms.

[0028] It is noted that bottom periphery 24 is exposed to the etchingconditions utilized to remove material 16 during the etch of material16, but the low concentration of reactive components of the etching gas,and the high pressure within the reactor, together result in material 16being removed much more rapidly than is material within opening 20. Theselectivity for material 16 can be enhanced by utilizing openings 20having a high critical dimension, and accordingly methodology of thepresent invention can work particularly well for openings having anaspect ratio of at least about 3, even better if the aspect ratio is atleast about 6, better if the aspect ratio is at least about 6.5, andbetter yet if the aspect ratio is at least about 7.

[0029] It is found that a suitable exposure time for removing 325angstroms of material 16 from over mass 14 is from about 60 seconds toabout 3 minutes in applications in which material 16 comprises siliconoxynitride and mass 14 comprises BPSG. Also, it is found that less than50 angstroms of material will be etched from a monocrystalline substrate12 exposed at a bottom of an opening 20 having a width “W” of 0.3microns, and a depth “D” of about 2 microns during such exposure timeand under preferred exposure conditions of the present invention. In aparticular embodiment, the initial width “W” of opening 20 is 0.3microns, the initial depth “D” is 2 microns, and 320 angstroms ofmaterial 16 is removed from over mass 14 while extending depth “D” byonly from about 0.005 microns to about 0.007 microns into amonocrystalline silicon substrate 12.

[0030] A further advantage of methodology of the present invention isthat such can avoid increasing width “W” by any significant amountduring the removal of material 16. In particular embodiments, etchingconditions of the present invention can remove at least 250 angstroms ofthickness “X” of material 16 (FIG. 3) from over mass 14 and yet extendthe width “W” of the opening by no more than about 0.010 microns. Inparticular embodiments, the thickness “X” is reduced by at least about300 angstroms, or at least about 320 angstroms, and yet the width “W” ofopening 20 is not extended by more than 0.010 microns (100 angstroms).In particular aspects of the invention, the width is extend by fromabout 5 nanometers to about 7 nanometers.

[0031] Exemplary processes of the present invention include applicationsother than those discussed above. For instance, in particular aspectsthe invention includes methods in which a top surface treatment isutilized at relatively high pressures (at least about 300 mTorr, and inparticular applications at least about 1000 mTorr, and in furtherapplications from about 300 mTorr to about 4000 mTorr) and low reactivegas concentrations (less than 4.5% by volume, more preferably less than2% by volume, and even more preferably less than 1% by volume) toaccomplish spot planarization across a surface of a semiconductorsubstrate. Specifically, it is found that the combination of highpressure and low reactive gas concentrations can remove peaks andvalleys from across a semiconductor substrate to planarize the surface.In a particular application, a layer of in situ p-type dopedpolycrystalline silicon (polysilicon) is exposed to a reactive gascomprising O₂ and a low concentration of CF₄, at a pressure of about1000 mTorr, to reduce a thickness of the polysilicon from 2200 Å to 1600Å. Microwave power utilized in the etch is 1500 W. The etching not onlyreduces the thickness of the polysilicon, but also removes surfacedefects, and specifically can remove dimples that are 800 Å deep in theinitial (2200 Å thick) polysilicon. The etching can occur with little orno power bias (e.g., radiofrequency bias) in order to be relativelyisotropic.

[0032] Particular aspects of the present invention can resemble priorart cleaning procedures. A distinction between etching of the particularaspects of the present invention and the prior art cleaning proceduresis that typically only some of a material is removed in the etches,whereas all of a material is typically removed in a cleaning procedure.

[0033] In compliance with the statute, the invention has been describedin language more or less specific as to structural and methodicalfeatures. It is to be understood, however, that the invention is notlimited to the specific features shown and described, since the meansherein disclosed comprise preferred forms of putting the invention intoeffect. The invention is, therefore, claimed in any of its forms ormodifications within the proper scope of the appended claimsappropriately interpreted in accordance with the doctrine ofequivalents.

1. A semiconductor processing method comprising exposing a semiconductorsubstrate to etching conditions which include subjecting exposedsurfaces of the substrate to a gas having components therein which arereactive with the exposed surfaces; and wherein a total concentration ofsuch components within the gas is less than 4.5%, by volume.
 2. Thesemiconductor processing method of claim 1 wherein the exposed surfacescomprise a material; and wherein the etching removes only some of thematerial exposed to the etch.
 3. The semiconductor processing method ofclaim 1 wherein the etching occurs in a reactor, and wherein a pressureto which the substrate is exposed within the reactor is maintained to atleast about 300 mTorr during the etching.
 4. The semiconductorprocessing method of claim 1 wherein the etching occurs in a reactor,and wherein a pressure to which the substrate is exposed within thereactor is maintained to at least about 1000 mTorr during the etching.5. The semiconductor processing method of claim 1 wherein the etchingoccurs in a reactor, and wherein a pressure to which the substrate isexposed within the reactor is maintained to from about 300 mTorr toabout 4,000 mTorr during the etching.
 6. The semiconductor processingmethod of claim 1 wherein the total concentration of the components isless than 2%, by volume.
 7. The semiconductor processing method of claim1 wherein the total concentration of the components is less than 1% byvolume.
 8. The semiconductor processing method of claim 1 wherein thecomponents include fluorine-containing molecules.
 9. The semiconductorprocessing method of claim 1 wherein the components include NF₃.
 10. Thesemiconductor processing method of claim 1 wherein the semiconductorsubstrate has an opening extending therein; wherein the opening has adepth and a width; and wherein the opening has an aspect ratio of atleast about
 3. 11. The semiconductor processing method of claim 10wherein the opening has an aspect ratio of at least about
 6. 12. Thesemiconductor processing method of claim 10 wherein the opening has anaspect ratio of at least about 6.5.
 13. The semiconductor processingmethod of claim 10 wherein the opening has an aspect ratio of at leastabout
 7. 14. A semiconductor processing method, comprising: providing asemiconductor substrate having an opening extending therein; the openinghaving a depth and a width; and exposing the substrate to reactive ionetching conditions which comprise subjecting exposed surfaces of thesubstrate to a gas having components therein which are reactive with theexposed surfaces, and wherein a total concentration of such componentswithin the gas is less than 4.5%, by volume; wherein the etchingconditions comprise exposing the substrate to a bias of from about 50watts to about 2000 watts in a reactive ion etch plasma reactor, whilemaintaining a pressure within the reactor at from about 300 mTorr toabout 4,000 mTorr.
 15. The semiconductor processing method of claim 14wherein the bias is from about 350 watts to about 400 watts.
 16. Thesemiconductor processing method of claim 14 wherein the totalconcentration of the components is less than 2%, by volume.
 17. Thesemiconductor processing method of claim 14 wherein the totalconcentration of the components is less than 1%, by volume.
 18. Thesemiconductor processing method of claim 14 wherein the componentsinclude fluorine-containing molecules.
 19. The semiconductor processingmethod of claim 14 wherein the components include NF₃.
 20. Asemiconductor processing method, comprising: providing a semiconductorsubstrate having a first mass, a second mass over the first mass, and anopening extending through the first mass and into the second mass, thesecond mass having a thickness and the opening having a depth; and whilea bottom periphery of the opening is exposed, subjecting the substrateto etching conditions which remove at least 250 Å from the thickness ofthe second mass and which extend the depth of the opening by no morethan 50 Å.
 21. The semiconductor processing method of claim 20 whereinthe etching conditions comprise subjecting exposed surfaces of thesubstrate to a gas having components therein which are reactive with thefirst mass, and wherein a total concentration of such components withinthe gas is less than 4.5%, by volume.
 22. The semiconductor processingmethod of claim 21 wherein the total concentration of the components isless than 2%, by volume.
 23. The semiconductor processing method ofclaim 21 wherein the total concentration of the components is less than1%, by volume.
 24. The semiconductor processing method of claim 21wherein the components include fluorine-containing molecules.
 25. Thesemiconductor processing method of claim 21 wherein the componentsinclude NF₃.
 26. The semiconductor processing method of claim 20 whereinthe etching conditions comprise exposing the substrate to a bias of fromabout 50 watts to about 500 watts in a reactive ion etch plasma reactor,while maintaining a pressure within the reactor at from about 300 mTorrto about 1,000 mTorr.
 27. The semiconductor processing method of claim26 wherein the bias is from about 350 watts to about 400 watts.
 28. Thesemiconductor processing method of claim 26 wherein the etchingconditions comprise subjecting exposed surfaces of the substrate to agas having components therein which are reactive with the first mass,and wherein a total concentration of such components within the gas isless than 4.5%, by volume.
 29. The semiconductor processing method ofclaim 28 wherein the total concentration of the components is less than2%, by volume.
 30. The semiconductor processing method of claim 28wherein the total concentration of the components is less than 1%, byvolume.
 31. The semiconductor processing method of claim 28 wherein thecomponents include fluorine-containing molecules.
 32. The semiconductorprocessing method of claim 28 wherein the components include NF₃. 33.The semiconductor processing method of claim 20 wherein the opening hasan aspect ratio of at least about
 3. 34. The semiconductor processingmethod of claim 20 wherein the opening has an aspect ratio of at leastabout
 6. 35. The semiconductor processing method of claim 20 wherein theopening has an aspect ratio of at least about 6.5.
 36. The semiconductorprocessing method of claim 20 wherein the opening has an aspect ratio ofat least about
 7. 37. The semiconductor processing method of claim 20wherein the exposure to the etching conditions removes at least 300 Åfrom the thickness of the second mass.
 38. The semiconductor processingmethod of claim 20 wherein the exposure to the etching conditionsremoves at least 320 Å from the thickness of the second mass.
 39. Thesemiconductor processing method of claim 20 wherein the second mass issubstantially entirely removed from over the first mass during theexposure to the etching conditions.
 40. The semiconductor processingmethod of claim 20 wherein the opening extends through the second massand terminates proximate or within a third mass prior to the exposing tothe etching conditions.
 41. The semiconductor processing method of claim40 wherein the first mass comprises borophosphosilicate glass, thesecond mass comprises an antireflective coating, and the third masscomprises silicon.
 42. The semiconductor processing method of claim 40wherein the first mass comprises borophosphosilicate glass, the secondmass comprises DARC, and the third mass comprises silicon.
 43. Thesemiconductor processing method of claim 40 wherein the first masscomprises borophosphosilicate glass, the second mass comprises siliconoxynitride, and the third mass comprises silicon.
 44. The semiconductorprocessing method of claim 43 wherein the third mass comprisesmonocrystalline silicon.
 45. A semiconductor processing method,comprising: providing a semiconductor substrate having a first mass, asecond mass over the first mass, and an opening extending through thefirst mass and into the second mass, the second mass having a thicknessand the opening having a width; and without providing a protectivematerial over a bottom periphery of the opening, subjecting thesubstrate to etching conditions which remove at least 250 Å from thethickness of the second mass and which extend the width of the openingby no more than about 100 Å.
 46. The semiconductor processing method ofclaim 45 wherein the etching conditions comprise subjecting exposedsurfaces of the substrate to a gas having components therein which arereactive with the first mass, and wherein a total concentration of suchcomponents within the gas is less than 4.5%, by volume.
 47. Thesemiconductor processing method of claim 46 wherein the totalconcentration of the components is less than 2%, by volume.
 48. Thesemiconductor processing method of claim 46 wherein the totalconcentration of the components is less than 1%, by volume.
 49. Thesemiconductor processing method of claim 46 wherein the componentsinclude fluorine-containing molecules.
 50. The semiconductor processingmethod of claim 46 wherein the components include NF₃.
 51. Thesemiconductor processing method of claim 45 wherein the etchingconditions comprise exposing the substrate to a bias of from about 50watts to about 2000 watts in a reactive ion etch plasma reactor, whilemaintaining a pressure within the reactor at from about 300 mTorr toabout 4,000 mTorr.
 52. The semiconductor processing method of claim 51wherein the bias is from about 350 watts to about 400 watts.
 53. Thesemiconductor processing method of claim 52 wherein the etchingconditions comprise subjecting exposed surfaces of the substrate to agas having components therein which are reactive with the first mass,and wherein a total concentration of such components within the gas isless than 4.5%, by volume.
 54. The semiconductor processing method ofclaim 53 wherein the total concentration of the components is less than2%, by volume.
 55. The semiconductor processing method of claim 53wherein the total concentration of the components is less than 1%, byvolume.
 56. The semiconductor processing method of claim 53 wherein thecomponents include fluorine-containing molecules.
 57. The semiconductorprocessing method of claim 53 wherein the components include NF₃. 58.The semiconductor processing method of claim 45 wherein the opening hasan aspect ratio of at least about
 3. 59. The semiconductor processingmethod of claim 45 wherein the opening has an aspect ratio of at leastabout
 6. 60. The semiconductor processing method of claim 45 wherein theopening has an aspect ratio of at least about 6.5.
 61. The semiconductorprocessing method of claim 45 wherein the opening has an aspect ratio ofat least about
 7. 62. The semiconductor processing method of claim 45wherein the exposure to the etching conditions removes at least 300 Åfrom the thickness of the second mass.
 63. The semiconductor processingmethod of claim 45 wherein the exposure to the etching conditionsremoves at least 320 Å from the thickness of the second mass.
 64. Thesemiconductor processing method of claim 45 wherein the second mass issubstantially entirely removed from over the first mass during theexposure to the etching conditions; and wherein the exposure to theetching conditions.
 65. The semiconductor processing method of claim 45wherein the exposing to the etching conditions extends the width of theopening by no more than 50 Å.
 66. The semiconductor processing method ofclaim 45 wherein the exposing to the etching conditions extends thewidth of the opening by no more than 10 Å.
 67. The semiconductorprocessing method of claim 45 wherein the exposing to the etchingconditions extends a depth of the opening by no more than 50 Å.
 68. Thesemiconductor processing method of claim 67 wherein the opening extendsthrough the second mass and terminates proximate or within a third massprior to the exposing to the etching conditions which extend the depthof the opening by no more than 50 Å.
 69. The semiconductor processingmethod of claim 68 wherein the first mass comprises borophosphosilicateglass, the second mass comprises silicon oxynitride, and the third masscomprises silicon.
 70. The semiconductor processing method of claim 68wherein the third mass comprises monocrystalline silicon.
 71. Asemiconductor processing method, comprising: providing a semiconductorsubstrate having a first material, second material and third material;the second material being over the first material, and the thirdmaterial being over the second material; the third material having athickness; the substrate having an opening extending through the secondand third materials and to proximate a surface of the first material;the opening having a depth and a width; and exposing the substrate toreactive ion etching conditions which comprise subjecting exposedsurfaces of the substrate to a gas having components therein which arereactive with the second and third materials, and wherein a totalconcentration of such components within the gas is less than 4.5%, byvolume.
 72. The semiconductor processing method of claim 71 wherein thefirst material comprises monocrystalline silicon, the second materialcomprises borophosphosilicate glass, and the third material comprisessilicon oxynitride.
 73. The semiconductor processing method of claim 71wherein the total concentration of the components is less than 2%, byvolume.
 74. The semiconductor processing method of claim 71 wherein thetotal concentration of the components is less than 1%, by volume. 75.The semiconductor processing method of claim 71 wherein the componentsinclude fluorine-containing molecules.
 76. The semiconductor processingmethod of claim 71 wherein the components include NF₃.
 77. Thesemiconductor processing method of claim 71 wherein the etchingconditions comprise exposing the substrate to a bias of from about 50watts to about 2000 watts in a reactive ion etch plasma reactor, whilemaintaining a pressure within the reactor at from about 300 mTorr toabout 4,000 mTorr.
 78. The semiconductor processing method of claim 77wherein the bias is from about 350 watts to about 400 watts.
 79. Thesemiconductor processing method of claim 77 wherein the totalconcentration of the components is less than 2%, by volume.
 80. Thesemiconductor processing method of claim 77 wherein the totalconcentration of the components is less than 1%, by volume.
 81. Thesemiconductor processing method of claim 77 wherein the componentsinclude fluorine-containing molecules.
 82. The semiconductor processingmethod of claim 77 wherein the components include NF₃.
 83. Thesemiconductor processing method of claim 71 wherein the opening has anaspect ratio of at least about
 3. 84. The semiconductor processingmethod of claim 71 wherein the opening has an aspect ratio of at leastabout
 6. 85. The semiconductor processing method of claim 71 wherein theopening has an aspect ratio of at least about 6.5.
 86. The semiconductorprocessing method of claim 71 wherein the opening has an aspect ratio ofat least about
 7. 87. The semiconductor processing method of claim 71wherein the exposure to the etching conditions removes at least 250 Åfrom the thickness of the third material and extends the depth of theopening by no more than 50 Å.
 88. The semiconductor processing method ofclaim 71 wherein the exposure to the etching conditions removes at least300 Å from the thickness of the third material and extends the depth ofthe opening by no more than 50 Å.
 89. The semiconductor processingmethod of claim 71 wherein the exposure to the etching conditionsremoves at least 320 Å from the thickness of the third material andextends the depth of the opening by no more than 50 Å.
 90. Thesemiconductor processing method of claim 71 wherein the exposure to theetching conditions removes at least 250 Å from the thickness of thethird material and extends the width of the opening by no more thanabout 100 Å.
 91. The semiconductor processing method of claim 71 whereinthe exposure to the etching conditions removes at least 320 Å from thethickness of the third material, extends the depth of the opening by nomore than 50 Å, and extends the width of the opening by no more thanabout 100 Å.